1. Field
This disclosure relates in general to circuit designs, and in particular to an improvement in the design of IEEE 1149.1 Tap interfaces of ICs and core circuits for improved communication of test, debug, emulation, programming, and general purpose I/O operations.
Today's ICs may contain many embedded 1149.1 Tap architectures (Tap domains). Some of these TAP domains are associated with intellectual property (IP) core circuits within the IC, and serve as access interfaces to test, debug, emulation, and programming circuitry within the IP cores. Other TAP domains may exist in the IC which are not associated with cores but rather to circuitry in the IC external of the cores. Further, the IC itself will typically contain a TAP domain dedicated for operating the boundary scan register associated with the input and output terminals of the ICs, according to IEEE std 1149.1.
FIG. 1 illustrates a simple example of an IEEE 1149.1 Tap domain 102. The Tap domain includes a Tap controller 104, an instruction register (IR) 106, at least two data registers (DR) 108, and multiplexer circuitry 110. The Tap domain interface consists of a TDI input, a TCK input, a TMS input, a TRST input, and a TDO output. In response to TCK and TMS control inputs to Tap controller 104, the Tap controller outputs control to capture data into and shift data through either the IR 106 from TDI to TDO or a selected DR 108 from TDI to TDO. The data shifted into IR 106 is updated and output on bus 114 to other circuits, and the data shifted into a DR 108 is updated and output on bus 112 to other circuits. DR 108 may also capture data from other circuits on bus 112 and IR 106 may capture data from other circuits on bus 114. In response to a TRST input to the Tap controller 104, the TAP controller, IR and DR are reset to known states. The structure and operation of IEEE 1149.1 Tap domain architectures like that of FIG. 1 are well known.
FIG. 2 illustrates the state diagram of the Tap controller 104. All IEEE 1149.1 standard Tap controllers operate according to this state diagram. State transitions occur in response to TMS input and are clocked by the TCK input. The IEEE 1149.1 Tap state diagram is well known.
FIG. 3 illustrates an example system where a number of Tap domain 102 interfaces of ICs 306-312 or embedded cores 306-312 within ICs are connected together serially, via their TDI and TDO terminals, to form a scan path 302 from TDI 304 to TDO 306. Each Tap domain 102 of the ICs/cores 306-312 are also commonly connected to TCK 314, TMS 316, and TRST 318 inputs. The scan path's TDI 304, TDO 306, TCK 314, TMS 316, and TRST 318 signals are coupled to a controller, which can serve as a test, debug, emulation, in-system-programming, and/or other application controller. While only four Tap domains 102 of ICs/cores 306-312 are shown, any number of IC/core Tap domains may exist in scan path 302, as indicated by dotted line 322. The scan path 302 arrangement of IC/core Tap domains is well known in the industry.
As seen in FIG. 3, if data is to be input to Tap domain 102 of IC/core 312 from controller 320 it must serially pass through all leading Tap domains of ICs/cores 306-310. Further, if data is to be output from Tap domain 102 IC/core 306 to controller 320 it must pass through all trailing Tap domains of ICs/cores 308-312. Thus a data input and output latency exists between Tap domains of ICs/cores in scan path 302 and controller 320. As will be seen later, the present disclosure provides a way to eliminate this data input and output latency by making use of the direct TMS 316 and/or TCK 314 connections between the Tap Domains of ICs/cores 306-312 and controller 320. Having a direct connection for data input and output between the controller 320 and the Tap domains 102, via the TMS and/or TCK connections, provides improved data communication throughput during test, debug, emulation, in-circuit-programming, and/or other type of operations. Further, using the direct TCK and/or TMS connections for data input and output between controller 320 and Tap domains 102 only involves the controller and the targeted Tap domain. Non-targeted Tap domains are not aware of or affected by the direct TMS and/or TCK communication.